1. Field of the Invention
The present invention relates to a method for fabricating a Complementary Metal Oxide Semiconductor ("CMOS") Thin Film Transistor ("TFT"). More particularly, the present invention relates to fabricating a CMOS TFT with a simplified method which eliminates the ion implantation and annealing steps used in present methods.
2. State of the Art
The development of new portable electronic products, such as notebook computers and personal interface devices, is currently receiving a great deal of attention in the consumer products market. Substantial research and development have been focused in the field of active matrix liquid-crystal displays. Active matrix displays generally consist of flat panels of liquid crystals or electroluminescent materials which are switched "on" and "off" by electric fields. Every liquid crystal picture element ("pixel") is charged by thin film transistors ("TFTs"). One of the most common components in the circuit for the liquid crystal display is the inverter, which has a CMOS structure constructed with a pair of n-type and p-type TFTs.
Although both polysilicon and amorphous silicon may be used in the fabrication of TFTs, a polysilicon semiconductor layer generally provides greater mobility of electrons and holes than does amorphous silicon. Furthermore, the CMOS structure can be easier to construct with polysilicon since the n-type and p-type TFTs can be formed by the same implant and anneal process. The CMOS inverter constructed with polysilicon TFTs also offers excellent characteristics in terms of operating frequency and power consumption.
In the fabrication of a TFT, the semiconductor-layer source and drain regions are formed by introducing an impurity element into the semiconductor layer (see U.S. Pat. No. 5,514,879 issued May 7, 1996 to Yamazaki). The controlled introduction of impurities enable good transistor characteristics. Typically, the introduction of impurities for a CMOS TFT requires two masking and implantation steps. As shown in FIG. 26, a substrate 202 is coated with a layer of oxide 204. A non-doped polysilicon layer 206 is applied to the oxide layer 204, and a resist layer 208 is applied to the non-doped polysilicon layer 206 in a predetermined pattern. The non-doped polysilicon layer 206 is then etched to form a non-doped polysilicon ledge 210, as shown in FIG. 27. A portion of the non-doped polysilicon ledge 210 is masked with a first mask 212 and an n-type impurity is introduced into the unmasked portion of the non-doped polysilicon ledge 210 to form an n-type area 214, as shown in FIG. 28. The first mask 212 is removed and a second mask 216 is applied to the non-doped polysilicon ledge 210 so as to cover the n-type area 214 and a portion 220 of the non-doped polysilicon ledge 210. A p-type impurity is introduced to the unmasked portion of the non-doped polysilicon ledge 210 to form a p-type area 218, as shown in FIG. 29. The second mask 216 then is removed to form a fundamental CMOS TFT gate structure 222 with the portion 220 acting as an insulating barrier between the n-type area 214 and the p-type area 218, as shown in FIG. 30.
The impurities can be introduced by thermal diffusion or ion implantation. By using thermal diffusion, the impurities are introduced from the surface of the semiconductor layer. By using ion implantation, impurity ions are implanted into the semiconductor layer. The ion implantation method provides a more precise control with respect to the total impurity concentration and depth that the impurities can be implanted into the semiconductor layer, and thus allows impurities to be implanted into a shallow, thin film. Furthermore, ion implantation can be performed at low temperatures. For the above reasons, ion implantation is a preferred technique for introducing impurities into a semiconductor layer in the fabrication process of the TFT.
In the above-described fabrication process of the TFT, impurities are implanted by a conventional ion implantation apparatus using an ion beam having a diameter of only several millimeters. When the ions are to be implanted over a large substrate using the above conventional ion implantation apparatus, it is necessary to either move the substrate mechanically or scan the ion beam electrically over the substrate since the area of the substrate is larger than the diameter of the ion beam. The necessity of having a mechanical moving means for the ion beam causes a problem in that the ion implantation apparatus becomes complicated, large, and expensive.
One technique for solving the above problem, wherein ions can be easily implanted into a large area, is an ion shower-doping method. According to this technique, ions generated by using a plasma discharge are dispersed in a cone shape and accelerated at a low voltage without mass separation to implant in the substrate. Although this technique allows ions to be implanted simultaneously over a large portion of or the entire semiconductor layer, it does not result in uniform implantation.
Once the implantation is complete, the structure is annealed at about 600.degree. C. to activate the impurities. However, the temperature of annealing is detrimental to any temperature-sensitive portion of the entire structure.
Therefore, it would be advantageous to develop a technique to form a CMOS TFT which eliminates the need for introducing impurities during the fabrication of the CMOS TFT, while using state-of-the-art semiconductor device fabrication techniques employing known equipment, process steps, and materials.